This invention relates to a programmable logic device (PLD) architecture for accommodating specialized circuitry, such as a high-speed serial interface. More particularly, this invention relates to a programmable logic device architecture that allows the same die design to be used for different models within a family of PLDs, where the different models may or may not have specialized circuitry or such specialized circuitry may differ.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (Extended Attachment Unit Interface) standard and other standards. However, not all users of programmable logic devices require a high-speed serial interface, even among users having otherwise identical requirements for programmable logic functionality. Moreover, even among users who require a high-speed serial interface, some users may have enhanced requirements for such an interface, including, e.g., wider data rate support or more channels. Up to now, such a family of programmable logic devices would have at least three different members (even more when the availability of models of different size is considered), developed as different integrated circuit dies, increasing both cost and development times.
Other types of specialized circuitry, sometimes know as “hard logic” or “IP” blocks, are also provided on programmable logic devices, such as multipliers, digital signal processing blocks, phase-locked loops and delay-locked loops, etc. Similar considerations apply to those other types of specialized circuitry as well—i.e., different models of the same family may provide different capabilities with respect to one or more of those other types of specialized circuitry.
It would be desirable to be able to provide a family of programmable logic devices with different levels of support for specialized circuitry—from no support through enhanced support—with reduced development cost and times.